1. Field of the Invention
This application relates to semiconductor memory devices, and more particularly, to semiconductor memory devices with a shared open bit line sense amplifier architecture.
2. Description of the Related Art
In a dynamic random access memory (DRAM), design considerations such as the arrangement of memory cells, each including a transistor and a capacitor, and the arrangement of sense amplifiers that sense and amplify data output from each memory cell are significant in determining the area and the performance of the DRAM. In general, a memory cell array including a sense amplifier is arranged according to an open bit line method or a folded bit line method.
FIG. 1 illustrates the open bit line method, in which a memory cell MC is positioned at each intersection of a word line WL and a bit line BL to maximize the density of each memory cell MC and minimize the area of a chip. If the minimum design dimension is F, it is possible to manufacture a memory cell with an area of 4F2. However, since each sense amplifier SA must be designed to be arranged inside the pitch of a bit line BL, the design rules for sense amplifiers SA are tight, reducing flexibility in the design of the layout of the sense amplifiers SA. Furthermore, since a pair of bit lines BL connected to the sense amplifier SA are not arranged in the same cell array block, one side of the pair of the bit lines BL may be affected by noise generated in one cell array block, while the other side of the pair is not. Thus, a semiconductor memory device fabricated according to the open bit line method is vulnerable to noise.
FIG. 2 illustrates a relaxed open bit line method in which a memory cell MC is positioned at each intersection of a word line WL and a bit line BL and each sense amplifier SA is arranged inside the pitch of two bit lines BL. It is easier to design the layout of the sense amplifier SA using the relaxed open bit line method than using the open bit line method. However, it is still difficult to design the layout of the sense amplifier SA using the relaxed open bit line method. In addition, a semiconductor memory device manufactured according to the relaxed open bit line method is vulnerable to noise similar to one manufactured according to the open bit line method.
FIG. 3 illustrates a folded bit line method in which a sense amplifier SA is arranged inside the pitch of four bit lines BL, and thus, it is easier to design than a sense amplifier using the open bit line method. In addition, since a pair of bit lines BL connected to the sense amplifier SA are installed in the same cell array block, both sides of the pair of the bit lines BL are affected by noise generated in the cell array. Thus, a semiconductor memory device manufactured using the folded bit line method is more immune to noise. However, a memory cell MC manufactured according to the folded bit line method has an area of 8F2. The area of the memory cell MC may be double that of the memory cell MC manufactured according to the open bit line method, increasing the required chip area.
As described above, the area of a memory cell array manufactured according to the open bit line method is reduced, but the memory cell array is vulnerable to noise. In contrast, a memory cell array manufactured according to the folded bit line method is more immune to noise, but the area of a memory cell array is increased.
Since the trend in DRAMs is to increase capacity, the open bit line method has been used in arranging memory cells to reduce the area of each memory cell array. Accordingly, a method of arranging sense amplifiers that reduces noise is required.